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128-Position I2C Compatible Digital Resistor AD5246
FEATURES
128-position End-to-end resistance 5 k, 10 k, 50 k, 100 k Ultracompact SC70-6 (2 mm x 2.1 mm) package I2C(R) compatible interface Full read/write of wiper register Power-on preset to midscale Single supply 2.7 V to 5.5 V Low temperature coefficient 45 ppm/C Low power, IDD = 3 A typical Wide operating temperature -40C to +125C Evaluation board available
FUNCTIONAL BLOCK DIAGRAM
VDD
SCL SDA I2C INTERFACE A W B
03875-0-001
WIPER REGISTER
GND
Figure 1.
APPLICATIONS
Mechanical potentiometer replacement in new designs Transducer adjustment of pressure, temperature, position, chemical, and optical sensors RF amplifier biasing Automotive electronics adjustment Gain control and offset adjustment
1
Note: The terms digital potentiometer, VR, and RDAC are used interchangeably in this document.
GENERAL OVERVIEW
The AD5246 provides a compact 2 mm x 2.1 mm packaged solution for 128-position adjustment applications. This device performs the same electronic adjustment function as a variable resistor. Available in four different end-to-end resistance values (5 k, 10 k, 50 k, 100 k), these low temperature coefficient devices are ideal for high accuracy and stability variable resistance adjustments. The wiper settings are controllable through the I2C compatible digital interface, which can also be used to read back the present wiper register control word. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC1 latch. Operating from a 2.7 V to 5.5 V power supply and consuming 3 A allows for usage in portable battery-operated applications.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD5246 TABLE OF CONTENTS
Electrical Characteristics--5 k Version ...................................... 3 Electrical Characteristics--10 k, 50 k, 100 k Versions ....... 4 Timing Characteristics--5 k, 10 k, 50 k, 100 k Versions 5 Absolute Maximum Ratings............................................................ 6 Typical Performance Characteristics ............................................. 7 Test Circuits..................................................................................... 10 I2C Interface..................................................................................... 11 Operation......................................................................................... 12 Programming the Variable Resistor ......................................... 12 I2C Compatible 2-Wire Serial Bus............................................ 13 Level Shifting for Bidirectional Interface ................................ 13 ESD Protection ........................................................................... 13 Terminal Voltage Operating Range.......................................... 14 Maximum Operating Current .................................................. 14 Power-Up Sequence ................................................................... 14 Layout and Power Supply Bypassing ....................................... 14 Constant Bias to Retain Resistance Setting............................. 15 Evaluation Board ........................................................................ 15 Pin Configuration and Function Descriptions........................... 16 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD5246 ELECTRICAL CHARACTERISTICS--5 k VERSION
Table 1. VDD = 5 V 10% or 3 V 10%; VA = +VDD; -40C < TA < +125C; unless otherwise noted
Parameter DC CHARACTERISTICS--RHEOSTAT MODE Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient RWB RESISTOR TERMINALS Voltage Range4 Capacitance5 B Capacitance5 W Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance5 POWER SUPPLIES Power Supply Range Supply Current Power Dissipation6 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 7 Bandwidth -3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Density Symbol R-DNL R-INL RAB RAB/T RWB Conditions RWB RWB TA = 25C Wiper = No Connect Code=0x00, VDD = 5 V Code=0x00, VDD = 2.7 V Min -1.5 -4 -30 Typ1 0.1 0.75 45 75 150 GND f = 1 MHz, Measured to GND, Code = 0x40 f = 1 MHz, Measured to GND, Code = 0x40 45 60 1 2.4 0.8 2.1 0.6 1 5 2.7 VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = +5 V 10%, Code = Midscale RAB = 5 k, Code = 0x40 VA = 1 V rms, VB = 0 V, f = 1 kHz VA = 5 V, 1 LSB Error Band RWB = 2.5 k, RS = 0 3 0.01 1.2 0.05 1 6 5.5 8 40 0.02 Max +1.5 +4 +30 150 400 VDD Unit LSB LSB % ppm/C V pF pF nA V V V V A pF V A W %/% MHz % s nV/Hz
VB, W CB CW ICM VIH VIL VIH VIL IIL CIL VDD RANGE IDD PDISS PSSR BW_5K THDW tS eN_WB
VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VIN = 0 V or 5 V
1 2
Typical specifications represent average readings at 25C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 Code = 0x7F. 4 Resistor terminals A and W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 7 All dynamic characteristics use VDD = 5 V.
Rev. 0 | Page 3 of 20
AD5246 ELECTRICAL CHARACTERISTICS--10 k, 50 k, 100 k VERSIONS
Table 2. VDD = 5 V 10% or 3 V 10%; VA = VDD; -40C < TA < +125C; unless otherwise noted
Parameter DC CHARACTERISTICS--RHEOSTAT MODE Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient RWB RESISTOR TERMINALS Voltage Range4 Capacitance5 B Capacitance5 W Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance5 POWER SUPPLIES Power Supply Range Supply Current Power Dissipation6 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 7 Bandwidth -3 dB Total Harmonic Distortion VW Settling Time (10 k/50 k/100 k) Resistor Noise Voltage Density Symbol R-DNL R-INL RAB RAB/T RWB Conditions RWB, VA = No Connect RWB, VA = No Connect TA = 25C Wiper = No Connect Code=0x00, VDD = 5 V Code=0x00, VDD = 2.7 V Min -1 -2 -20 Typ1 0.1 0.25 45 75 150 GND f = 1 MHz, Measured to GND, Code = 0x40 f = 1 MHz, measured to GND, Code = 0x40 45 60 1 2.4 0.8 2.1 0.6 1 5 2.7 VIH = 5 V or VIL = 0 V VIH = 5 V or VIL = 0 V, VDD = 5 V VDD = +5 V 10%, Code = Midscale RAB = 10 k/50 k/100 k, Code = 0x40 VA =1 V rms, f = 1 kHz, RAB = 10 k VA = 5 V 1 LSB Error Band RWB = 5 k, RS = 0 3 0.01 600/100/40 0.05 2 9 5.5 8 40 0.02 Max +1 +2 +20 150 400 VDD Unit LSB LSB % ppm/C V pF pF nA V V V V A pF V A W %/% kHz % s nV/Hz
VB, W CB CW ICM VIH VIL VIH VIL IIL CIL VDD RANGE IDD PDISS PSSR BW THDW tS eN_WB
VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VIN = 0 V or 5 V
1 2
Typical specifications represent average readings at +25C and VDD = 5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 Code = 0x7F. 4 Resistor terminals A and W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 7 All dynamic characteristics use VDD = 5 V.
Rev. 0 | Page 4 of 20
AD5246 TIMING CHARACTERISTICS--5 k, 10 k, 50 k, 100 k VERSIONS
Table 3. VDD = 5 V 10% or 3 V 10%; VA = VDD; -40C < TA < +125C; unless otherwise noted
Parameter I2C INTERFACE TIMING CHARACTERISTICS2, 3 (Specifications Apply to All Parts) SCL Clock Frequency tBUF Bus Free Time between STOP and START tHD;STA Hold Time (Repeated START) tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setup Time for Repeated START Condition tHD;DAT Data Hold Time tSU;DAT Data Setup Time tF Fall Time of Both SDA and SCL Signals tR Rise Time of Both SDA and SCL Signals tSU;STO Setup Time for STOP Condition Symbol Conditions Min Typ1 Max Unit
fSCL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
400 1.3 After this period, the first clock pulse is generated. 0.6 1.3 0.6 0.6 100 300 300 0.6
kHz s s s s s s ns ns ns s
50 0.9
1 2
Typical specifications represent average readings at 25C and VDD = 5 V. Guaranteed by design and not subject to production test. 3 See timing diagrams (Figure 25, Figure 26, Figure 27) for locations of measured values.
Rev. 0 | Page 5 of 20
AD5246 ABSOLUTE MAXIMUM RATINGS
Table 4. TA = 25C, unless otherwise noted1
Parameter VDD to GND VA, VW to GND Terminal Current, Ax-Bx, Ax-Wx, Bx-Wx Pulsed2 Continuous Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Thermal Resistance3 JA: SC70-6 Value -0.3 V to +7 V VDD 20 mA 5 mA 0 V to VDD + 0.3 V -40C to +125C 150C -65C to +150C 300C 340C/W
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 3 Package power dissipation = (TJMAX - TA)/JA.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 6 of 20
AD5246 TYPICAL PERFORMANCE CHARACTERISTICS
1.0 0.8 0.6 VDD = 2.7V TA = 25C RAB = 10k 0.5 0.4
-40C +25C +85C +125C VDD = 2.7V RAB = 10k
RHEOSTAT MODE INL (LSB)
RHEOSTAT MODE DNL (LSB)
0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0
0.4 0.2 0 -0.2 -0.4 -0.6
03875-0-020
TA = -40C, +25C, +85C, +125C
VDD = 5.5V
-0.8 -1.0 0 16 32 64 80 48 CODE (Decimal) 96 112 128
16
32
48 64 80 CODE (Decimal)
96
112
128
Figure 2. R-INL vs. Code vs. Supply Voltages
Figure 5. R-DNL vs. Code vs. Temperature
0.5 0.4 0.3 TA = 25C RAB = 10k
RHEOSTAT MODE INL (LSB) FSE, FULL-SCALE ERROR (LSB)
0
-0.5 VDD = 5.5V, VA = 5.5V -1.0
RHEOSTAT MODE DNL (LSB)
0.2 0.1 0 -0.1 -0.2 -0.3
03875-0-021
VDD = 2.7V
-1.5
VDD = 5.5V
-2.0 VDD = 2.7V, VA = 2.7V
03875-0-024
-2.5
-0.4 -0.5 0 16 32 64 80 48 CODE (Decimal) 96 112
128
-3.0 -40
-25
-10
5
20 35 50 65 TEMPERATURE (C)
80
95
110 125
Figure 3. R-DNL vs. Code vs. Supply Voltages
Figure 6. Full-Scale Error vs. Temperature
1.0 0.8 0.6
RHEOSTAT MODE INL (LSB)
TA = +85C TA = -40C
1.50
1.25
ZSE, ZERO-SCALE ERROR (LSB)
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16 32 64 80 48 CODE (Decimal) 96 TA = -40C
TA = +25C
03875-0-022
1.00 VDD = 5.5V, VA = 5.5V
TA = +25C
TA = +125C
0.75
0.50
TA = +125C
112
128
0 -40 -25
-10
5
20 35 50 65 TEMPERATURE (C)
80
95
110 125
Figure 4. R-INL vs. Code vs. Temperature
Figure 7. Zero-Scale Error vs. Temperature
Rev. 0 | Page 7 of 20
03875-0-025
TA = +85C
0.25
VDD = 2.7V, VA = 2.7V
03875-0-023
AD5246
100 DIGITAL INPUTS = 0V CODE = 0x40 IDD, SUPPLY CURRENT (A) 10 VDD = 5.5V
GAIN (dB)
0 -6 -12 -18 -24 -30 -36 -42
03875-0-026
0x40 0x20 0x10 0x08 0x04 0x02 0x01
1
VDD = 2.7V 0.1
-48 -54 -60 1k 10k 100k FREQUENCY (Hz) 1M
03875-0-029
0.01 -40 -25 -10
5
20 35 50 65 TEMPERATURE (C)
80
95
110
125
10M
Figure 8. Supply Current vs. Temperature
Figure 11. Gain vs. Frequency vs. Code, RAB = 10 k
500 400 RHEOSTAT MODE TEMPCO (ppm/C) 300 200 100 0 -100 -200 -300 -400 -500 0 16 32 48 64 80 CODE (Decimal) 96 112
TA = -40C to +125C
03875-0-027
0
VDD = 2.7V RAB = 10k
TA = -40C to +85C
-6 -12 -18
GAIN (dB)
0x40 0x20 0x10 0x08 0x04 0x02 0x01
-24 -30 -36 -42 -48 -54 -60 1k
128
10k
100k FREQUENCY (Hz)
1M
10M
Figure 9. Rheostat Mode Tempco RWB/T vs. Code
Figure 12. Gain vs. Frequency vs. Code, RAB = 50 k
0 -6 -12 -18 0x40 0x20
0 -6 -12 0x40 0x20 0x10 0x08 0x04 0x02 0x01
0x10 0x08 0x04 0x02 0x01 GAIN (dB)
-18 -24 -30 -36 -42
03875-0-028
GAIN (dB)
-24 -30 -36 -42 -48 -54 -60 1k
-48 -54 -60 1k 10k 100k FREQUENCY (Hz) 1M
03875-0-031
10k
100k FREQUENCY (Hz)
1M
10M
10M
Figure 10. Gain vs. Frequency vs. Code, RAB = 5 k
Figure 13. Gain vs. Frequency vs. Code, RAB = 100 k
Rev. 0 | Page 8 of 20
03875-0-030
AD5246
0 -6 -12 -18 100k 10k 50k 5k
VDD = 5.5V VB = 0V
TA = 25C RAB = 10k FCLK = 100kHz
GAIN (dB)
-24 -30 -36 -42 -48
VW
5V CLK
03875-0-032
0V
03875-0-006
-54 -60 1k 10k 100k FREQUENCY (Hz) 1M
10M
1s/DIV
Figure 14. -3 dB Bandwidth @ Code = 0x80
Figure 17. Digital Feedthrough
0.30
A - VDD = 5.5V CODE = 0x55 B - VDD = 5.5V CODE = 0x7F C - VDD = 2.7V CODE = 0x55 D - VDD = 2.7V CODE = 0x7F
TA = 25C
0.25
VDD = 5.5V VB = 0V CODE 0x40 to 0x3F
TA = 25C RAB = 10k
0.20
IDD (A)
0.15
0.10
VW
A B
03875-0-033
C 0 1k D 10k 100k FREQUENCY (Hz)
1M
200ns/DIV
Figure 15. IDD vs. Frequency
Figure 18. Midscale Glitch, Code 0x40 to 0x3F
360
300 VDD = 2.7V
TA = 25C RAB = 50k CODE = 0x00
VDD = 5.5V VB = 0V CODE 00H TO 7FH
TA = 25C RAB = 10k IW = 50A
240
RWB ()
180
120 VDD = 5.5V
03875-0-008
VW
1
60
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
40s/DIV
VBIAS (V)
Figure 16. RWB vs. VBIAS vs. VDD
Figure 19. Large Signal Settling Time
Rev. 0 | Page 9 of 20
03875-0-005
03875-0-007
0.05
AD5246 TEST CIRCUITS
Figure 20 to Figure 24 define the test conditions used in the
product Specification tables.
DUT W B VMS
03875-0-004
IW
DUT W B ISW
RSW =
0.1V ISW
CODE = 0x00 0.1V
03876-0-029
Figure 20. Test Circuit for Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
VDD TO GND
Figure 23. Test Circuit for Incremental ON Resistance
V+ = VDD 10% PSRR (dB) = 20 LOG PSS (%/%) = VMS V MS% V DD%
03875-0-009
DUT VDD V+ B W
(V MS ) DD
V
DUT W B ICM
NO CONNECT
Figure 21. Test Circuit for Power Supply Sensitivity (PSS, PSSR) Figure 24. Test Circuit for Common-Mode Leakage Current
DUT VIN
10k W B 10k +15V
OP27
VOUT
03875-0-010
2.5V
-15V
Figure 22. Test Circuit for Gain vs. Frequency
Rev. 0 | Page 10 of 20
03875-0-012
VCM
AD5246 I2C INTERFACE
Table 5. Write Mode
S 0 1 0 1 1 1 0 W A X D6 D5 D4 D3 D2 D1 D0 A P Slave Address Byte Data Byte
Table 6. Read Mode
S 0 1 0 1 1 Slave Address Byte 1 0 R A 0 D6 D5 D4 D3 Data Byte D2 D1 D0 A P
S = Start Condition. P = Stop Condition. A = Acknowledge. X = Don't Care.
W = Write. R = Read. D6, D5, D4, D3, D2, D1, D0 = Data Bits.
t8
SCL
t9
t2
t6 t2 t3 t8 t9 t4 t7 t5 t10
SDA
03875-0-019
t1 P S S P
Figure 25. I2C Interface, Detailed Timing Diagram
1 SCL SDA 0 1 0 1 1 1 0 R/W
9
1
9
1
X
D6
D5
D4
D3
D2
D1
D0
03875-0-014
03875-0-013
START BY MASTER
FRAME 1 SLAVE ADDRESS BYTE
ACK BY AD5246
FRAME 2 DATA BYTE
ACK BY AD5246
STOP BY MASTER
Figure 26. Writing to the RDAC Register
1 SCL 0 1 0 1 1 1 0 R/W
9
1
9
SDA
0
D6
D5
D4
D3
D2
D1
D0
START BY MASTER
FRAME 1 SLAVE ADDRESS BYTE
ACK BY AD5246
FRAME 2 RDAC REGISTER
NO ACK BY MASTER STOP BY MASTER
Figure 27. Reading from the RDAC Register
Rev. 0 | Page 11 of 20
AD5246 OPERATION
The AD5246 is a 128-position, digitally controlled variable resistor (VR) device. An internal power-on preset places the wiper at midscale during power-on, which simplifies the default condition recovery at power-up. The general equation determining the digitally programmed output resistance between W and B is
RWB(D) =
D x RAB + 2 x RW 128
(1)
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between terminals A and B is available in 5 k, 10 k, 50 k, and 100 k. The final two or three digits of the part number determine the nominal resistance value, e.g., 10 k = 10, 50 k = 50. The nominal resistance (RAB) of the VR has 128 contact points accessed by the wiper terminal, plus the B terminal contact. The 7-bit data in the RDAC latch is decoded to select one of the 128 possible settings. Assuming a 10 k part is used, the wiper's first connection starts at the B terminal for data 0x00. Since there is a 50 wiper contact resistance, such a connection yields a minimum of 100 (2 x 50 ) resistance between terminals W and B. The second connection is the first tap point, which corresponds to 178 (RWB = RAB/128 + RW = 78 + 2 x 50 ) for data 0x01. The third connection is the next tap point, representing 256 (2 x 78 + 2 x 50 ) for data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,100 (RAB + 2 x RW). Figure 28 shows a simplified diagram of the equivalent RDAC circuit.
Ax
where D is the decimal equivalent of the binary code loaded in the 7-bit RDAC register, RAB is the end-to-end resistance, and RW is the wiper resistance contributed by the on resistance of the internal switch. In summary, if RAB = 10 k and the A terminal is open-circuited, the output resistance RWB shown in Table 7 will be set for the indicated RDAC latch codes.
Table 7. Codes and Corresponding RWB Resistance
D (Dec.) 127 64 1 0 RWB () 10,100 5,100 178 100 Output State Full Scale (RAB + 2 x RW) Midscale 1 LSB Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition, a finite wiper resistance of 100 is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. Typical device-to-device matching is process lot dependent and may vary by up to 30%. Since the resistance element is processed in thin film technology, the change in RAB with temperature has a very low 45 ppm/C temperature coefficient.
D6 D5 D4 D3 D2 D1 D0
RS RS
Wx
RDAC LATCH AND RS DECODER
Bx
03875-0-015
Figure 28. AD5246 Equivalent RDAC Circuit
Rev. 0 | Page 12 of 20
AD5246
I2C COMPATIBLE 2-WIRE SERIAL BUS
The first byte of the AD5246 is a slave address byte (see Table 5 and Table 6). It has a 7-bit slave address and a R/W bit. The seven MSBs of the slave address are 0101110 followed by 0 for a write command or 1 to place the device in read mode. The 2-wire I2C serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 26). The following byte is the slave address byte, which consists of the 7-bit slave address followed by an R/W bit (this bit determines whether data will be read from or written to the slave device). The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master will read from the slave device. On the other hand, if the R/W bit is low, the master will write to the slave device. 2. In write mode, after acknowledgement of the slave address byte, the next byte is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Table 5). In read mode, after acknowledgment of the slave address byte, data is received over the serial bus in sequences of nine clock pulses (a slight difference from the write mode where eight data bits are followed by an acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 27). When all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master will pull the SDA line high during the tenth clock pulse to establish a STOP condition (see Figure 26). In read mode, the master will issue a No Acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the tenth clock pulse, which goes high to establish a STOP condition (see Figure 27). A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing the part only once. For example, after the RDAC has acknowledged its slave address in write mode, the RDAC output will update on each successive byte. If different instructions are needed, write/read mode has to start again with a new slave address and data byte. Similarly, a repeated read function of the RDAC is also allowed.
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
While most legacy systems may be operated at one voltage, a new component may be optimized at another. When two systems operate the same signal at two different voltages, proper level shifting is needed. For instance, one can use a 3.3 V E2PROM to interface with a 5 V digital potentiometer. A level shifting scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer can be stored to and retrieved from the E2PROM. Figure 29 shows one of the implementations. M1 and M2 can be any N channel signal FETs, or if VDD falls below 2.5 V, M1 and M2 can be low threshold FETs such as the FDV301N.
VDD1 = 3.3V RP RP G SDA1 SCL1 3.3V S M1 D G S M2 D 5V
03875-0-011
VDD2 = 5V RP RP
SDA2 SCL2
E2PROM
AD5246
3.
Figure 29. Level Shifting for Operation at Different Potentials
ESD PROTECTION
All digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in Figure 30 and Figure 31. This applies to the digital input pins SDA and SCL.
340 LOGIC
4.
GND
Figure 30. ESD Protection of Digital Pins
B,W
03875-0-002
03875-0-003
GND
Figure 31. ESD Protection of Resistor Terminals
Rev. 0 | Page 13 of 20
AD5246
TERMINAL VOLTAGE OPERATING RANGE
The AD5246 VDD and GND power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on terminals B and W that exceed VDD or GND will be clamped by the internal forward biased diodes (see Figure 32).
VDD
POWER-UP SEQUENCE
Since the ESD protection diodes limit the voltage compliance at terminals B and W (see Figure 32), it is important to power VDD/GND before applying any voltage to terminals B and W; otherwise, the diode will be forward biased such that VDD will be powered unintentionally and may affect the rest of the user's circuit. The ideal power-up sequence is in the following order: GND, VDD, digital inputs, and then VB/VW. The relative order of powering VB and VW and the digital inputs is not important as long as they are powered after VDD/GND.
B
LAYOUT AND POWER SUPPLY BYPASSING
W
GND
It is a good practice to employ a compact, minimum lead-length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is a good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 F to 0.1 F disc or chip ceramic capacitors. Low ESR 1 F to 10 F tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see Figure 34). Note that the digital ground should also be joined remotely to the analog ground at one point to minimize the ground bounce.
Figure 32. Maximum Terminal Voltages Set by VDD and GND
MAXIMUM OPERATING CURRENT
At low code values, the user should be aware that due to low resistance values, the current through the RDAC may exceed the 5 mA limit. In Figure 33, a 5 V supply is placed on the wiper, and the current through terminals W and B is plotted with respect to code. A line is also drawn denoting the 5 mA current limit. Note that at low code values (particularly for the 5 k and 10 k options), the current level increases significantly. Care should be taken to limit the current flow between W and B in this state to a maximum continuous current of 5 mA and a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contacts can occur.
100.00
03875-0-016
VDD
VDD C1 C3 + 0.1F 10F
AD5246
Figure 34. Power Supply Bypassing
10.00 5mA CURRENT LIMIT RAB = 5k 1.00 RAB = 10k RAB = 50k 0.10 RAB = 100k 0.01 0 16 32 64 80 48 CODE (Decimal) 96 112
03875-0-034
IWB CURRENT (mA)
128
Figure 33. Maximum Operating Current
Rev. 0 | Page 14 of 20
03875-0-017
GND
AD5246
CONSTANT BIAS TO RETAIN RESISTANCE SETTING
For users who desire nonvolatility but cannot justify the additional cost for the EEMEM, the AD5246 may be considered as a low cost alternative by maintaining a constant bias to retain the wiper setting. The AD5246 was designed specifically with low power in mind, which allows low power consumption even in battery-operated systems. The graph in Figure 35 demonstrates the power consumption from a 3.4 V 450 mAhr Li-ion cell phone battery, which is connected to the AD5246. The measurement over time shows that the device draws approximately 1.3 A and consumes negligible power. Over a course of 30 days, the battery was depleted by less than 2%, the majority of which is due to the intrinsic leakage current of the battery itself.
110% 108% 106% TA = 25C
This demonstrates that constantly biasing the pot is not an impractical approach. Most portable devices do not require the removal of batteries for the purpose of charging. Although the resistance setting of the AD5246 will be lost when the battery needs replacement, such events occur rather infrequently such that this inconvenience is justified by the lower cost and smaller size offered by the AD5246. If and when total power is lost, the user should be provided with a means to adjust the setting accordingly.
EVALUATION BOARD
An evaluation board, along with all necessary software, is available to program the AD5246 from any PC running Windows(R) 98, Windows 2000, or Windows XP(R). The graphical user interface, as shown in Figure 36 is straightforward and easy to use. More detailed information is available in the user manual, which comes with the board.
BATTERY LIFE DEPLETED
104% 102% 100% 98% 96% 94% 92% 90% 0 5 10 15 DAYS 20 25 30
03875-0-035
Figure 36. AD5246 Evaluation Board Software
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03876-0-061
Figure 35. Battery Operating Life Depletion
AD5246 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD 1 GND 2
AD5246
TOP VIEW
6B 5W
03875-0-018
SCL 3 (Not to Scale) 4 SDA
Figure 37. Pin Function Descriptions, 6-Lead SC70
Table 8. AD5246 Pin Function Descriptions
Pin No. 1 2 3 4 5 6 Mnemonic VDD GND SCL SDA W B Description Positive Power Supply. Digital Ground. Serial Clock Input. Positive edge triggered. Serial Data Input/Output. W Terminal. B Terminal.
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AD5246 OUTLINE DIMENSIONS
2.00 BSC
6
5 2
4
1.25 BSC
1 3
2.10 BSC
PIN 1 1.30 BSC 1.00 0.90 0.70 0.65 BSC 1.10 MAX 0.22 0.08 0.30 0.15 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203AB SEATING PLANE 8 4 0
0.10 MAX
0.46 0.36 0.26
Figure 38. 6-Lead Thin Shrink Small Outline Transistor [SC70] (KS-6) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5246BKS5-R2 AD5246BKS5-RL7 AD5246BKS10-R2 AD5246BKS10-RL7 AD5246BKS50-R2 AD5246BKS50-RL7 AD5246BKS100-R2 AD5246BKS100-RL7 AD5246EVAL
1
RAB (k) 5 5 10 10 50 50 100 100 See Note 1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Package Description 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 6-lead SC70 Evaluation Board
Package Option KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6 KS-6
Branding D16 D16 D1D D1D D1C D1C D1A D1A
The evaluation board is shipped with the 10 k RAB resistor option; however, the board is compatible with all available resistor value options.
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AD5246 NOTES
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AD5246 NOTES
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AD5246 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03875-0-9/03(0)
Rev. 0 | Page 20 of 20

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